The following technology is known in relation to semiconductor storage devices. Namely, semiconductor storage devices are known that have a local bit line (LBL) laid out for each sector corresponding to each global bit line (GBL). In such semiconductor storage devices, a sector select transistor connects an LBL to a GBL, and ON/OFF controls the sector select transistor of the sector corresponding to the sector select line. Plural word lines (WL) are provided so as to intersect with each LBL, and memory cells are laid out so as to correspond to the intersection locations between each LBL and WL. The memory cells include memory transistors that connect source lines to corresponding LBLs, and that are ON/OFF controlled by the corresponding WL. Charging transistors connect LBLs to a charging line. Charging gate lines ON/OFF control the charging transistors. A pre-charge potential is applied to an LBL by a charging transistor adopting an ON state.
Moreover, semiconductor storage devices are known that are equipped with flash memory arrays configured from plural non-volatile memory cells laid out in a matrix pattern. In such semiconductor storage devices, a current source for reading supplies a current in parallel to each of the main bit lines during read operation. A column switch circuit connects a main bit line from out of plural main bit lines that is specified by an address signal to a common bit line. During read operation, a sense amplifier is input with a read signal transmitted by a common bit line, compares the potential of the main bit lines connected to the common bit line against a reference potential, and detects whether or not a current has flowed between the drain and the source of the non-volatile memory cell to be read.
Semiconductor storage devices are also known that are equipped with a pre-charge stage including a read charge transistor capable of applying a specific read potential to a bit line in order to read data, and a read discharge transistor that connects bit line not selected during reading to a ground potential. In these semiconductor storage devices, the non-selected bit lines are held at the ground potential, and, after being preparatory charged, the selected bit lines adopt a floating state and are connected to the sense amplifier.